1. Field of the Invention
The present invention relates to debugging units of integrated circuits (ICs). More specifically, the present invention relates to debugging units, which can act as bus masters to better control various elements of an integrated circuit.
2. Discussion of Related Art
Due to advancing semiconductor processing technology, integrated circuits (ICs) have greatly increased in functionality and complexity. For example, circuits and systems, which once required several ICs, are being combined into a single IC. However, with the increasing functionality of ICs, testing and debugging of ICs becomes increasingly difficult.
FIG. 1 is a simplified schematic diagram of a conventional integrated circuit (IC) 110 coupled to an external controller 105. IC 110 includes a JTAG interface 120 coupled to functional blocks 130 and 140. JTAG interface 120 is an industry standard serial interface (IEEE Std 1149.1).
Typically, external controller 105 uses JTAG interface 120 to retrieve state information in IC 110. Typically, the storage units, e.g. flip-flops, of IC 110 are connected in a serial scan chain so that the output terminal of a storage element is coupled to the input terminal of the next storage element in the serial scan chain. JTAG interface 120 can serially retrieve the logic level stored in each of the storage elements of IC 110 by clocking the serial scan chain of storage elements and reading the last storage element of the serial scan chain. JTAG interface 120 provides the retrieved information to external controller 105. In some versions if IC 110, JTAG interface 120 can also serially write data into the storage elements of IC 110. Thus, external controller 105 can configure the storage elements of IC 110 to set up specific test conditions to debug IC 110. However, because the storage elements are serially chained together, JTAG interface 120 serially writes data to every storage element even if the logic level stored in only one storage element needs to be changed.
As explained above, ICs are becoming increasingly complex and therefore the number of storage elements within ICs is rapidly increasing. With such large numbers of storage elements, using serial scan chains for debugging becomes costly due to the overhead required to couple all the registers to the scan chain and the overhead. Hence, there is a need for a method or structure to rapidly write and read information into the storage elements of an IC for debugging the IC.
Accordingly, the present invention includes a debugging unit which uses a multi-master general purpose bus within an IC to read from and write to storage elements within the IC. Specifically, the storage elements of the IC are mapped into the address space of the general purpose bus. The debugging unit can operate as a bus master and read from or write to the storage elements of the integrated circuit directly. Thus, the integrated circuit can be rapidly configured for testing and debugging.